Description and objectives
Studying the architecture, organization and use of the newest general purpose (micro)processors currently on the market, and the latest research developments in computer architecture. Architectures exploiting instruction-level parallelism (ILP), thread-level and task-level parallelism are treated. Starting from basic architecture concepts we will end with discussing the latest commercial processors (e.g., Pentium 4 multi-core, EPIC processors like Itanium, and embedded processors such as the TriMedia), and academic processors (like TRIPS).
This course also treats how processors can be combined in a multiprocessing platform, e.g. by using a Network-on-Chip. Interprocessor communication issues will be dealt with. Furthermore new code generation techniques needed for exploiting ILP will be treated. Special emphasis will be on quantifying design decisions in terms of performance and cost.
Topics:Basic principles (like instruction set design), pipelining and its consequences; VLIW (very long instruction word) architectures, Superpipelined, Superscalar, SIMD (single instruction, multiple data, used in vector and sub-wordparallel processors) and MIMD (multiple instruction, multiple data) architectures; SMT (Simultaneous Multi-Threading); Out-of-order and speculative execution; Branch prediction; Data (value) prediction; Design of advanced memory hierarchies; Memory coherency and consistency; Multi-threading; Exploiting task-level and instruction-level parallelism; Inter-processor communication models; Input and output; Network Communication Architecture; and Networks-on-Chip.
|Computer Architecture: A Quantitative Approach; 4th ed.|
John L. Hennessy and David A. Patterson
Morgan Kaufmann Publishers
Slides** will be added and updated during the course period **
- Overview slides (including preliminary schedule)
- Topic 1: Computer Systems Overview
- Topic 2: Crash course on MIPS
- MIPS instruction set
- MIPS design 1: single cycle and multi-cycle implementations
- MIPS design 2: pipelined implementation
- Topic 3: Instruction-set design
- Topic 4: Instruction-Level Parallel (ILP) architectures
- The best of both worlds: EPIC or the Itanium architecture
- Topic 5: Exploiting ILP with Software approaches
- Topic 6: SMT: simultaneous multi-threading
- Guest lecture by Wouter van der Put: Time Predictability of a Computer System
- Topic 7: Multi-Processors
- part 1
- Including Synchronization, Memory Coherence, and Memory Consistency
- Topic 8 Caches and Memory Hierarchy;