Advanced Computer Architecture

Advanced Computer Architecture Slides

Course Content

Instruction set, memory management and hierarchy, input/output and buses, pipelining techniques, branch prediction, RISC architectures, VLIW architectures and specific compiling techniques, superscalar architectures, out of order execution, parallel architectures and multiprocessors.

Prerequisites

TSEA04 (Switching Theory and Logical Design),
TSEA19/20 (Computer Hardware and Architecture)

Reading Instructions

Introduction:
Outline, Basic computer architecture and organization, Basic functions of a computer and its main components, The von Neumann architecture, Historical perspective.
Some basic issues are recapitulated which are supposed to be known from previous courses.
(2.1, 2.2, 3.1, 3.2, 3.3, 3.4, 5.1, 5.3, 5.4, 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, Chapter 9, 10.1, 10.3, 14.1, 14.2, 14.3, 15.1, 15.2)

The Memory System and its Organization:
Memory hierarchy, Organization of internal memories, Cache memories, Memory Management.
(4.1, 4.2, 4.3, 7.3)

Instruction Pipelining:
Organization of pipelined units, Pipeline hazards, Reducing branch penalties, Branch prediction strategies.
(11.1, 11.2, 11.3, 11.4, 12.5)

Reduced Instruction Set Computer (RISC) Architectures:
An analysis of instruction execution for code generated from high-level language programs, Compiling for RISC architectures, Main characteristics of RISC architectures, RISC-CISC trade-offs.
(12.1, 12.2, 12.4, 12.8)

Superscalar Architectures:
Instruction level parallelism and machine parallelism, Hardware techniques for performance enhancement, Data dependencies, Policies for parallel instruction execution, Limitations of the superscalar approach.
(13.1, 13.2)

Very Large Instruction Word (VLIW) Architectures:
The VLIW approach - advantages and limitations. Compiling for VLIW architectures. The Merced (Itanium) architecture.
(13.7)

Architectures for Parallel Computation:
Parallel programms, Performance of parallel computers, A classification of computer architectures, Array processors, Multiprocessors, Multicomputers, Vector processors. Cache Coherence and the MESI Protocol.
(16.1, 16.2, 16.3, 16.6)

Architectures for Low Power Consumption: The Crusoe Processors
The Technology Behind Crusoe Processors.

Lectures

• Lecture 1.
• Lecture 2.
• Lecture 3.
• Lecture 4.
• Lecture 5.
• Lecture 6.
• Lecture 7.
• Lecture 8.
• Lecture 9.
• Lecture 10.
• Lecture 11.
• Lecture 12.
• Exam questions and reading instructions: part 1 (slides) and part two.