COMPUTER ARCHITECTURE AND ENGINEERING PPT,PDF
Instructor: Prof John Kubiatowicz
book: We will be using the second edition of Patterson and Hennessy's Computer Organization and Design book.
The "MIPS RISC Architecture" book will be essential for the project.
"Computer Architecture: A Quantitative Approach" is an excellent reference, but is not required for the course.
Instructor: Prof John Kubiatowicz
Expanded Description:
This course will give you an in-depth understanding of the inner-workings of modern digital computer systems and tradeoffs present at the hardware-software interface. You will get an understanding of the design process in the context of a complex hardware system and practical experience with computer-aided design tools. Topics include: Instruction set design, computer arithmetic, controller and datapath design, memory systems, input-output systems, networks interrupts and exceptions, pipelining, performance and cost analysis, computer architecture history, and a survey of advanced architectures. There will be a computer design project requiring 100+ hours. We will implement a major subset of the MIPS architecture to the gate level.book: We will be using the second edition of Patterson and Hennessy's Computer Organization and Design book.
The "MIPS RISC Architecture" book will be essential for the project.
"Computer Architecture: A Quantitative Approach" is an excellent reference, but is not required for the course.
Lec No. | Lecture Topic Click on lecture for WEB cast | Notes | |||
1 | Introduction, 5 components of a computer | ||||
2 | Review of MIPS ISA, Performance | ||||
3 | Logic Design, Technology & Delay Modeling | ||||
| First Sections | | |||
| Prerequisite Quiz: In class | | |||
4 | Performance and the Design process | ||||
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5 | High-Level design and FPGA | ||||
6 | Verilog (finished), Multiplication | ||||
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7 | [Homework quiz #2 at beginning of lecture] Single-Cycle Processor | ||||
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8 | Instruction Decode/Multicycle Processor | ||||
9 | Multiprogramming/Exceptions | ||||
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10 | Exceptions (continued), Pipelining | ||||
11 | [Homework quiz #3 at beginning of lecture] Pipelining (Continued) | ||||
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12 | Pipelining Control | ||||
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13 | Static Scheduling and compiler optimizations | ||||
14 | Compiler Optimizations (continued), Dynamic Scheduling | ||||
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15 | Tomasulo Scheduling | ||||
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16 | [Homework quiz #4 at beginning of lecture] Dynamic Scheduling (Con't), Speculation | ||||
17 | Speculation (Con't) | ||||
18 | Speculation (Finished), Memory Technology | ||||
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19 | Memory Technology | ||||
20 | Caches | ||||
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21 | Virtual Memory | ||||
22 | Buses and I/O | ||||
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23 | [Homework quiz #5 at beginning of lecture] I/O and Queueing theory | ||||
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24 | Queueing Theory, I/O arrays | ||||
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25 | Low Power Design, Intel Processors | ||||
26 | Quantum computing + Wrap-up Lecture: Look at all you have learned! | ||||
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